The inventive concept relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package by stacking a semiconductor chip, including through electrodes, on a semiconductor wafer.
Semiconductor products are being reduced in size while processing ever larger amount of data. Accordingly, semiconductor chips used in the semiconductor products need to be highly integrated and packaged as a single unit. The demand for size reduction not only accelerates the development of technologies related to chip-sized packages, but also, emphasizes the importance of packaging technologies that may improve the mechanical and electrical reliability when mounting semiconductor chips. In particular, when a semiconductor package is manufactured by stacking a plurality of semiconductor chips, the plurality of semiconductor chips may have a relatively large capacity, low power consumption, a high transmission rate, and may be highly efficient. When stacking the plurality of semiconductor chips, a micro-bump may be applied to a pin and a through electrode may be used to thus manufacture a small, high-integrated, and high capacity semiconductor package. But conventional approaches for manufacturing a semiconductor package having stacked semiconductor chips leave parts of the package susceptible to damage during the manufacturing process.